a substrate including a device layer, a handle substrate, and a buried insulator layer between the handle substrate and the device layer;

a first semiconductor layer on the device layer in a first device region, the first semiconductor layer comprising a III-V compound semiconductor material;

a second semiconductor layer on the device layer in a second device region, the second semiconductor layer comprising silicon;

a high-electron-mobility transistor including a gate structure on the first semiconductor layer; and

a second device structure including a doped region in the second semiconductor layer, the doped region and the second semiconductor layer defining a p-n junction.