US 11,784,088 B2
Isolation gap filling process for embedded dram using spacer material
Chieh-Jen Ku, Hillsboro, OR (US); Bernhard Sell, Portland, OR (US); Pei-Hua Wang, Beaverton, OR (US); Harish Ganapathy, Portland, OR (US); and Leonard C. Pipes, Beaverton, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Jan. 29, 2019, as Appl. No. 16/260,632.
Prior Publication US 2020/0243376 A1, Jul. 30, 2020
Int. Cl. H10B 12/00 (2023.01); H01L 21/762 (2006.01)
CPC H01L 21/76283 (2013.01) [H10B 12/01 (2023.02); H10B 12/20 (2023.02); H10B 12/50 (2023.02)] 9 Claims
OG exemplary drawing
 
1. A transistor, comprising:
a semiconductor channel with a first surface and a second surface opposite the first surface;
a source electrode coupled to the first surface of the semiconductor channel;
a drain electrode coupled to the first surface of the semiconductor channel;
a gate dielectric over the second surface of the semiconductor channel;
a gate electrode separated from the semiconductor channel by the gate dielectric;
an isolation trench adjacent to the semiconductor channel, the isolation trench comprising a spacer lining a surface of the isolation trench, and an isolation fill material, and the isolation trench extending entirely through the gate electrode;
an etch-stop layer beneath the gate electrode and beneath the isolation trench; and
a via in the etch-stop layer, the via in contact with a bottom surface of the gate electrode.