US 11,783,902 B2
Multi-state programming of memory cells
Karthik Sarpatwari, Boise, ID (US); and Nevil N. Gajera, Meridian, ID (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Mar. 30, 2022, as Appl. No. 17/709,102.
Application 17/709,102 is a continuation of application No. 16/993,831, filed on Aug. 14, 2020, granted, now 11,295,822.
Prior Publication US 2022/0223212 A1, Jul. 14, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. G11C 11/34 (2006.01); G11C 16/34 (2006.01); G11C 16/10 (2006.01); G11C 16/32 (2006.01); G11C 16/30 (2006.01); G11C 16/26 (2006.01)
CPC G11C 16/3404 (2013.01) [G11C 16/10 (2013.01); G11C 16/26 (2013.01); G11C 16/30 (2013.01); G11C 16/32 (2013.01)] 18 Claims
OG exemplary drawing
 
1. An apparatus, comprising:
a memory; and
circuitry configured to program a memory cell of the memory to one of four possible data states by:
applying a first voltage pulse to the memory cell, wherein the first voltage pulse has a first polarity; and
applying a second voltage pulse to the memory cell, wherein:
the second voltage pulse has a second polarity; and
the second voltage pulse is applied for a shorter duration than the first voltage pulse; and
wherein a magnitude of a threshold voltage distribution associated with a first one of the four possible data states is less than a magnitude of a threshold voltage distribution associated with a second one of the four possible data states.