CPC G11C 16/3404 (2013.01) [G11C 16/10 (2013.01); G11C 16/26 (2013.01); G11C 16/30 (2013.01); G11C 16/32 (2013.01)] | 18 Claims |
1. An apparatus, comprising:
a memory; and
circuitry configured to program a memory cell of the memory to one of four possible data states by:
applying a first voltage pulse to the memory cell, wherein the first voltage pulse has a first polarity; and
applying a second voltage pulse to the memory cell, wherein:
the second voltage pulse has a second polarity; and
the second voltage pulse is applied for a shorter duration than the first voltage pulse; and
wherein a magnitude of a threshold voltage distribution associated with a first one of the four possible data states is less than a magnitude of a threshold voltage distribution associated with a second one of the four possible data states.
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