CPC G11C 16/14 (2013.01) [G11C 16/0483 (2013.01); G11C 16/26 (2013.01); G11C 16/32 (2013.01); G11C 16/3431 (2013.01); H01L 27/1159 (2013.01)] | 30 Claims |
14. A memory device on an integrated circuit adapted with ephemeral data retention capability comprising:
an array of charge storage elements;
wherein each charge storage element in said array is characterized by an inherent leakage current and is configurable:
to store a first amount of charge corresponding to a first state corresponding to a first state representing a first data value; and
to store a second amount of charge corresponding to a second state representing a second data value;
a programming control circuit configured:
to program said array of charge storage elements to said second data value based on a first write operation;
to initiate and control a slow erase operation on said array, including at least a first mode in which a controlled erase charge is actively removed from a selected charge storage element over a controlled predetermined period and in the absence of a new second write operation for such selected charge storage element;
to actively impose erase bias voltages to said array of charge storage elements during said controlled predetermined period so that said controlled erase charge is removed from such elements in addition to charge lost to leakage current by such elements; and
to apply the smallest possible bias required to remove charge from the selected charge storage elements during said controlled predetermined period to achieve a target data retention time.
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