US 11,783,105 B2
Method and system for verifying a sorter
Simon Gaulter, Hertfordshire (GB); Thomas Ferrere, Hertfordshire (GB); Faizan Nazar, Hertfordshire (GB); and Sam Elliott, London (GB)
Assigned to Imagination Technologies Limited, Kings Langley (GB)
Filed by Imagination Technologies Limited, Kings Langley (GB)
Filed on Mar. 19, 2021, as Appl. No. 17/207,030.
Claims priority of application No. 2003988 (GB), filed on Mar. 19, 2020.
Prior Publication US 2021/0294949 A1, Sep. 23, 2021
Int. Cl. G06F 30/30 (2020.01); G06F 30/33 (2020.01)
CPC G06F 30/33 (2020.01) 19 Claims
OG exemplary drawing
 
1. A method of verifying a hardware design for a sorter, the sorter accepting base inputs each of a bit width m, the method comprising:
generating a modified version of the hardware design of the sorter accepting extended inputs with a bit width m+q; and
performing formal verification comprising:
implementing a constraint that q least significant bits of each input in a set of extended inputs represent a unique value; and
formally verifying aspects of the modified version of the hardware design of the sorter for the set of extended inputs.