CPC G06F 30/33 (2020.01) | 19 Claims |
1. A method of verifying a hardware design for a sorter, the sorter accepting base inputs each of a bit width m, the method comprising:
generating a modified version of the hardware design of the sorter accepting extended inputs with a bit width m+q; and
performing formal verification comprising:
implementing a constraint that q least significant bits of each input in a set of extended inputs represent a unique value; and
formally verifying aspects of the modified version of the hardware design of the sorter for the set of extended inputs.
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