US 11,783,104 B2
Apparatus and method for mapping foundational components during design porting from one process technology to another process technology
Chih-yuan Stephen Yu, San Jose, CA (US); Boh-Yi Huang, San Jose, CA (US); Chao-Chun Lo, San Jose, CA (US); and Xiang Guo, San Jose, CA (US)
Assigned to Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Jul. 14, 2022, as Appl. No. 17/865,084.
Application 17/865,084 is a continuation of application No. 17/239,000, filed on Apr. 23, 2021, granted, now 11,403,448.
Prior Publication US 2022/0414304 A1, Dec. 29, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 30/30 (2020.01); G06F 30/323 (2020.01); G06F 30/392 (2020.01); G06F 30/327 (2020.01); G06F 115/06 (2020.01)
CPC G06F 30/323 (2020.01) [G06F 30/327 (2020.01); G06F 30/392 (2020.01); G06F 2115/06 (2020.01)] 20 Claims
OG exemplary drawing
 
1. A method for migrating a circuit design from a first semiconductor fabrication process to a second semiconductor fabrication process comprising:
receiving the circuit design, wherein the circuit design comprises a gate-level netlist;
parsing the gate-level netlist one row at a time into one or more standard cells forming an application specific integrated circuit (ASIC) design;
forming a plurality of mapping tables having mapping rules for mapping the parsed one or more standard cells to equivalent target standard cells implemented in the second semiconductor fabrication process;
mapping the parsed one or more standard cells to the equivalent target standard cells using the plurality of mapping tables;
generating a target gate-level netlist describing the circuit design in terms of the equivalent target standard cells; and
outputting migrated physical layout of the circuit design for manufacturing under the second semiconductor fabrication process.