US 11,782,866 B2
Techniques to support mulitple interconnect protocols for an interconnect
Stephen R. Van Doren, Portland, OR (US); Rajesh M. Sankaran, Portland, OR (US); David A. Koufaty, Portland, OR (US); Ramacharan Sundararaman, Hillsboro, OR (US); and Ishwar Agarwal, Hillsboro, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Feb. 17, 2022, as Appl. No. 17/674,030.
Application 17/674,030 is a continuation of application No. 15/640,463, filed on Jul. 1, 2017, abandoned.
Prior Publication US 2022/0197847 A1, Jun. 23, 2022
Int. Cl. G06F 13/42 (2006.01); G06F 13/14 (2006.01); G06F 13/38 (2006.01)
CPC G06F 13/4234 (2013.01) [G06F 13/14 (2013.01); G06F 13/38 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An apparatus comprising:
an interface logic to receive message information, the message information comprising at least one of first information or second information;
a multi-protocol multiplexer coupled to the interface logic to receive at least one of the first information of a first interconnect protocol or the second information of a second interconnect protocol, the multi-protocol multiplexer to direct the at least one of the first information or the second information to physical layer circuitry; and
the physical layer circuitry coupled to the multi-protocol multiplexer, wherein the physical layer circuitry is to receive the at least one of the first information or the second information and output at least one packet on a link,
wherein:
for the first interconnect protocol, the physical layer circuitry is to receive the first information and output a first packet comprising the first information, the first interconnect protocol comprising a non-coherent protocol comprising a Peripheral Component Interconnect Express protocol; and
for the second interconnect protocol, the physical layer circuitry is to receive the second information and output a second packet comprising the second information, the second interconnect protocol comprising a coherent protocol, and for a third interconnect protocol, the physical layer circuitry further is to receive third information of the third interconnect protocol and output a third packet comprising the third information, the third interconnect protocol comprising a memory interconnect protocol.