CPC G06F 13/4234 (2013.01) [G06F 13/14 (2013.01); G06F 13/38 (2013.01)] | 20 Claims |
1. An apparatus comprising:
an interface logic to receive message information, the message information comprising at least one of first information or second information;
a multi-protocol multiplexer coupled to the interface logic to receive at least one of the first information of a first interconnect protocol or the second information of a second interconnect protocol, the multi-protocol multiplexer to direct the at least one of the first information or the second information to physical layer circuitry; and
the physical layer circuitry coupled to the multi-protocol multiplexer, wherein the physical layer circuitry is to receive the at least one of the first information or the second information and output at least one packet on a link,
wherein:
for the first interconnect protocol, the physical layer circuitry is to receive the first information and output a first packet comprising the first information, the first interconnect protocol comprising a non-coherent protocol comprising a Peripheral Component Interconnect Express protocol; and
for the second interconnect protocol, the physical layer circuitry is to receive the second information and output a second packet comprising the second information, the second interconnect protocol comprising a coherent protocol, and for a third interconnect protocol, the physical layer circuitry further is to receive third information of the third interconnect protocol and output a third packet comprising the third information, the third interconnect protocol comprising a memory interconnect protocol.
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