CPC G06F 12/0802 (2013.01) [G06F 2212/60 (2013.01); G06F 2212/72 (2013.01)] | 26 Claims |
1. An apparatus comprising:
a memory array configured as a cache memory having multiple cache lines;
an interface between the cache memory and at least one processor; and
a cache controller coupled to the cache memory, the cache controller configured to:
receive first data for entry in the cache memory;
randomly select one of the multiple cache lines of the cache memory for eviction;
evict second data from the randomly selected cache line of the cache memory; and
enter the first data in the randomly selected cache line of the cache memory, and
wherein the randomly selected cache line is a first cache line of the cache memory and the cache controller is further configured to:
receive the first data from a second cache line of the cache memory; and
enter the first data from the second cache line in the first cache line to provide at least two instances of the first data in the cache memory.
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