US 11,782,830 B2
Cache memory with randomized eviction
Amitava Majumdar, Boise, ID (US); Sandeep Krishna Thirumala, Boise, ID (US); Lingming Yang, Meridian, ID (US); Karthik Sarpatwari, Boise, ID (US); and Nevil N. Gajera, Meridian, ID (US)
Assigned to Micron Technologies, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Dec. 20, 2021, as Appl. No. 17/556,862.
Prior Publication US 2023/0195623 A1, Jun. 22, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 12/00 (2006.01); G06F 12/0802 (2016.01)
CPC G06F 12/0802 (2013.01) [G06F 2212/60 (2013.01); G06F 2212/72 (2013.01)] 26 Claims
OG exemplary drawing
 
1. An apparatus comprising:
a memory array configured as a cache memory having multiple cache lines;
an interface between the cache memory and at least one processor; and
a cache controller coupled to the cache memory, the cache controller configured to:
receive first data for entry in the cache memory;
randomly select one of the multiple cache lines of the cache memory for eviction;
evict second data from the randomly selected cache line of the cache memory; and
enter the first data in the randomly selected cache line of the cache memory, and
wherein the randomly selected cache line is a first cache line of the cache memory and the cache controller is further configured to:
receive the first data from a second cache line of the cache memory; and
enter the first data from the second cache line in the first cache line to provide at least two instances of the first data in the cache memory.