US 11,782,786 B1
Systems and methods for handling invalid floating-point operations without exceptions
Jeffrey S. Gilton, Cincinnati, OH (US); Matthew B. Pfenninger, Cincinnati, OH (US); and Serge Rosine, Cincinnati, OH (US)
Assigned to General Electric Company, Schenectady, NY (US)
Filed by General Electric Company, Schenectady, NY (US)
Filed on Mar. 17, 2022, as Appl. No. 17/697,465.
Int. Cl. G06F 11/07 (2006.01); G06F 9/30 (2018.01)
CPC G06F 11/0793 (2013.01) [G06F 9/3013 (2013.01); G06F 11/0721 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A device comprising:
one or more processors; and
one or more non-transitory memory modules communicatively coupled to the one or more processors and storing machine-readable instructions that, when executed, cause the one or more processors to at least:
determine whether an application software has called an application programming interface;
upon determination that the application software has called the application programming interface, determine whether one or more floating-point errors are recorded in a floating-point status register; and
upon determination that one or more floating-point errors are recorded in the floating-point status register, perform a predefined action for each type of floating-point error recorded in the floating-point status register.