| CPC G06F 9/4403 (2013.01) [G06F 12/0877 (2013.01); G06F 2212/603 (2013.01)] | 25 Claims |
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1. An apparatus comprising:
a memory array;
a cache; and
a control component coupled with the memory array and configured to cause the apparatus to:
identify, for a memory device, a candidate for a next command of a boot procedure associated with a host device based at least in part on a boot sequence stored in the memory array of the memory device;
transfer, to the cache of the memory device, first data stored in the memory array indicated by the candidate for the next command, the transferring based at least in part on a size of the first data to be transferred satisfying a size threshold, whether the first data to be transferred is static for each boot sequence of a plurality of boot sequences, or both, wherein the first data is static based at least in part on the first data being data that is transferred during each boot sequence of the plurality of boot sequences or being stored in a same location during each boot sequence of the plurality of boot sequences, or both;
receive, from the host device, a command that requests second data stored in the memory array as part of the boot procedure and based at least in part on transferring the first data;
identify that a first address of the first data stored in the cache is the same as a second address of the second data requested by the command; and
output, to the host device, the first data stored in the cache based at least in part on identifying that the first address of the first data stored in the cache is the same as the second address of the second data requested by the command.
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