CPC G06F 9/30145 (2013.01) [G06F 9/3836 (2013.01); G06F 9/449 (2018.02); G06F 9/468 (2013.01); G06F 16/9017 (2019.01)] | 24 Claims |
1. A processor comprising:
a decoder circuit to decode an instruction into a decoded instruction, the instruction comprising a pointer to a block of memory and an opcode to indicate an execution circuit is to cause insertion of an entry comprising an allocated object tag into a capability table for the pointer and provide a resultant of an index value for the entry in the capability table;
the execution circuit to execute the decoded instruction according to the opcode; and
a memory controller circuit to, in response to a request to access the block of memory through the pointer to the block of memory, allow access to the block of memory in response to validation of an allocated object tag in the pointer with the allocated object tag in the entry of the capability table that is indexed by the index value in the pointer.
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