US 11,782,716 B2
Hardware apparatuses, methods, and systems for individually revocable capabilities for enforcing temporal memory safety
Michael LeMay, Hillsboro, OR (US); Vedvyas Shanbhogue, Austin, TX (US); Deepak Gupta, Portland, OR (US); Ravi Sahita, Portland, OR (US); David M. Durham, Beaverton, OR (US); Willem Pinckaers, San Francisco, CA (US); and Enrico Perla, Centallo (IT)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Nov. 2, 2021, as Appl. No. 17/517,580.
Application 17/517,580 is a continuation of application No. 16/729,358, filed on Dec. 28, 2019, granted, now 11,163,569, issued on Nov. 2, 2021.
Prior Publication US 2022/0058023 A1, Feb. 24, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 9/30 (2018.01); G06F 9/38 (2018.01); G06F 9/448 (2018.01); G06F 9/46 (2006.01); G06F 16/901 (2019.01); G06F 9/455 (2018.01); G06F 12/14 (2006.01); G06F 21/52 (2013.01); G06F 21/79 (2013.01); G06F 9/35 (2018.01)
CPC G06F 9/30145 (2013.01) [G06F 9/3836 (2013.01); G06F 9/449 (2018.02); G06F 9/468 (2013.01); G06F 16/9017 (2019.01)] 24 Claims
OG exemplary drawing
 
1. A processor comprising:
a decoder circuit to decode an instruction into a decoded instruction, the instruction comprising a pointer to a block of memory and an opcode to indicate an execution circuit is to cause insertion of an entry comprising an allocated object tag into a capability table for the pointer and provide a resultant of an index value for the entry in the capability table;
the execution circuit to execute the decoded instruction according to the opcode; and
a memory controller circuit to, in response to a request to access the block of memory through the pointer to the block of memory, allow access to the block of memory in response to validation of an allocated object tag in the pointer with the allocated object tag in the entry of the capability table that is indexed by the index value in the pointer.