US 11,782,608 B1
Error information signaling for memory
Michael Dieter Richter, Ottobrunn (DE); Thomas Hein, Munich (DE); and Casto Salobrena Garcia, Munich (DE)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on May 20, 2022, as Appl. No. 17/749,966.
Int. Cl. G06F 3/06 (2006.01)
CPC G06F 3/0619 (2013.01) [G06F 3/0625 (2013.01); G06F 3/0655 (2013.01)] 25 Claims
OG exemplary drawing
 
1. A method, comprising:
detecting, by a memory device while in a power-saving mode in which one or more interfaces between the memory device and a host device are disabled, an error in a codeword stored in a memory array of the memory device;
indicating the error to the host device while the memory device is in the power-saving mode and based at least in part on detecting the error;
enabling the one or more interfaces based at least in part on indicating the error to the host device; and
transmitting, to the host device, error information associated with the error based at least in part on enabling the one or more interfaces.