US 12,439,838 B2
Resistive random access memory structure
Wen-Jen Wang, Tainan (TW); Chun-Hung Cheng, Kaohsiung (TW); and Chuan-Fu Wang, Miaoli County (TW)
Assigned to UNITED MICROELECTRONICS CORP., Hsin-Chu (TW)
Filed by UNITED MICROELECTRONICS CORP., Hsin-Chu (TW)
Filed on Jun. 13, 2024, as Appl. No. 18/741,808.
Application 18/741,808 is a continuation of application No. 17/159,160, filed on Jan. 27, 2021, granted, now 12,041,863.
Claims priority of application No. 202011604690.3 (CN), filed on Dec. 30, 2020.
Prior Publication US 2024/0334850 A1, Oct. 3, 2024
Int. Cl. H10N 70/20 (2023.01); H10B 63/00 (2023.01); H10N 70/00 (2023.01)
CPC H10N 70/8833 (2023.02) [H10B 63/00 (2023.02); H10N 70/023 (2023.02); H10N 70/063 (2023.02); H10N 70/841 (2023.02)] 15 Claims
OG exemplary drawing
 
1. A resistive random access memory (RRAM) structure, comprising:
a RRAM cell disposed on a substrate;
spacers disposed beside the RRAM cell, wherein widths of top surfaces of the spacers are equal to widths of bottom surfaces of the spacers, wherein the spacers have rectangular shape cross-sectional profiles; and
a dielectric layer blanketly covering the substrate and sandwiching the RRAM cell, wherein the spacers are located in the dielectric layer, and the dielectric layer comprises an ultra-low k dielectric layer.