US 12,439,837 B2
Via structure and methods of forming the same
Wei-Chieh Huang, Hsinchu County (TW); Jieh-Jang Chen, Hsinchu County (TW); Feng-Jia Shiu, Hsinchu County (TW); and Chern-Yow Hsu, Hsin-Chu County (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Jun. 10, 2024, as Appl. No. 18/738,161.
Application 18/738,161 is a continuation of application No. 17/977,317, filed on Oct. 31, 2022, granted, now 12,010,933.
Application 17/977,317 is a continuation of application No. 17/306,626, filed on May 3, 2021, granted, now 11,489,115, issued on Nov. 1, 2022.
Application 17/306,626 is a continuation of application No. 16/594,306, filed on Oct. 7, 2019, granted, now 10,998,498, issued on May 4, 2021.
Application 16/594,306 is a continuation of application No. 15/884,505, filed on Jan. 31, 2018, granted, now 10,439,135, issued on Oct. 8, 2019.
Claims priority of provisional application 62/583,866, filed on Nov. 9, 2017.
Prior Publication US 2024/0334847 A1, Oct. 3, 2024
Int. Cl. H10N 70/00 (2023.01); H01L 21/285 (2006.01); H01L 21/3105 (2006.01); H01L 21/311 (2006.01); H01L 21/321 (2006.01); H01L 21/768 (2006.01); H10B 63/00 (2023.01); H10N 70/20 (2023.01)
CPC H10N 70/8418 (2023.02) [H01L 21/28562 (2013.01); H01L 21/28568 (2013.01); H01L 21/31053 (2013.01); H01L 21/31144 (2013.01); H01L 21/3212 (2013.01); H01L 21/76879 (2013.01); H10B 63/80 (2023.02); H10N 70/021 (2023.02); H10N 70/063 (2023.02); H10N 70/231 (2023.02); H10N 70/826 (2023.02); H10N 70/8413 (2023.02); H10N 70/8828 (2023.02); H10N 70/8833 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
a substrate;
a bottom electrode in the substrate;
a dielectric layer over the bottom electrode and the substrate;
a conductive via through the dielectric layer, the conductive via extending to the bottom electrode and having a width-to-height ratio less than 1.0;
a chalcogenide glass layer over the conductive via; and
a top electrode over the chalcogenide glass layer,
wherein top surfaces of the bottom electrode and the substrate are coplanar.