| CPC H10N 70/8418 (2023.02) [H10B 63/24 (2023.02); H10N 70/011 (2023.02)] | 20 Claims |
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1. A device comprising:
a dielectric layer over a substrate;
a first bit line over the dielectric layer;
an insulating layer over the first bit line;
a second bit line over the insulating layer;
a hard mask layer over the second bit line;
a memory material extending over a sidewall of the first bit line, a sidewall of the insulating layer, a sidewall of the second bit line, and a sidewall of the hard mask layer;
a selector layer extending over the memory material;
a control word line extending over the selector layer and over the dielectric layer; and
a first via extending through the dielectric layer and contacting a bottom surface of the control word line.
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