| CPC H10N 60/81 (2023.02) [H10N 60/01 (2023.02); H10N 60/82 (2023.02); H10N 69/00 (2023.02)] | 10 Claims |

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1. A structure comprising:
a first device comprising a first chip and a second chip, the second chip having a first side with a plurality of bumps and a second side having a plurality of first superconducting lines;
a solder bonded layer attaching the first chip to a second side of the second chip opposite the first side;
a second device having a first side with a plurality of pads facing the plurality of bumps in the second chip and a second side of the second device opposite the first side having a plurality of second superconducting lines; and
a solder shield material surrounding the plurality of bumps and the plurality of pads, wherein the plurality of bumps on the second chip are bonded to the plurality of pads on the second device; and
the solder shield material is connected to the plurality of first superconducting lines of the first device and to the plurality of second superconducting lines of the second device.
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