| CPC H10N 50/80 (2023.02) [H10B 61/20 (2023.02); H10N 50/01 (2023.02)] | 20 Claims |

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1. A magnetic memory device, comprising:
a bottom electrode, a magnetic tunnel junction pattern, and a top electrode that are sequentially stacked on a substrate,
wherein the magnetic tunnel junction pattern comprises:
a free layer;
a pinned layer between the bottom electrode and the free layer; and
a tunnel barrier layer between the pinned layer and the free layer,
wherein, in a direction parallel to a top surface of the substrate, a middle portion of the pinned layer is wider than an upper portion of the pinned layer and is wider than a lower portion of the pinned layer.
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