| CPC H10K 59/1213 (2023.02) [H10D 30/6723 (2025.01); H10D 30/6743 (2025.01); H10D 30/6755 (2025.01); H10K 59/1216 (2023.02); H10K 59/131 (2023.02)] | 20 Claims |
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1. A display panel comprising:
a base layer comprising a display area and a non-display area;
a repair circuit disposed in the non-display area;
a pixel disposed in the display area and comprising a pixel circuit and a light emitting element electrically connected to the pixel circuit; and
a repair line electrically connected to the repair circuit and extending from the repair circuit to the pixel, the pixel circuit comprising:
a silicon transistor comprising a silicon semiconductor pattern comprising a first input area, a first channel area, and a first output area and a first gate disposed on the silicon semiconductor pattern and overlapping the first channel area;
an oxide transistor comprising a light shielding pattern disposed on the first gate and disposed on a same layer as a layer on which the repair line is disposed, an oxide semiconductor pattern disposed on the light shielding pattern and comprising a second input area, a second channel area, and a second output area, and a second gate disposed on the oxide semiconductor pattern and overlapping the second channel area; and
a bridge electrode disposed on a same layer as a layer on which the second gate is disposed, overlapping the repair line, and electrically connected to the light emitting element and the silicon transistor,
wherein the silicon semiconductor pattern of the silicon transistor and the oxide semiconductor pattern of the oxide transistor are disposed on different layers.
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