US 12,439,746 B1
Seal ring with inner setback wall for yield improvement
Christopher L. Boitnott, Redwood City, CA (US); Alejandro X. Levander, El Granada, CA (US); Cheuk Chi Lo, Belmont, CA (US); Chun-Ming Tang, Saratoga, CA (US); Patrick B. Bennett, San Leandro, CA (US); Peng Xu, Santa Clara, CA (US); To C. Tan, Redwood City, CA (US); and Yingkan Lin, San Jose, CA (US)
Assigned to Apple Inc., Cupertino, CA (US)
Filed by Apple Inc., Cupertino, CA (US)
Filed on Oct. 18, 2022, as Appl. No. 18/047,428.
Claims priority of provisional application 63/264,891, filed on Dec. 3, 2021.
Int. Cl. H10H 20/853 (2025.01); H10H 29/14 (2025.01); H10K 50/84 (2023.01); H10K 59/123 (2023.01); H10K 59/131 (2023.01)
CPC H10H 20/853 (2025.01) [H10H 29/142 (2025.01); H10K 50/84 (2023.02); H10K 59/123 (2023.02); H10K 59/131 (2023.02)] 21 Claims
OG exemplary drawing
 
1. A display panel comprising:
a semiconductor substrate;
a plurality of devices formed in a die area of the semiconductor substrate;
a build-up structure over the semiconductor substrate, the build-up structure including pixel wiring connected with the die area, and a seal ring laterally surrounding the pixel wiring;
an emission layer including an array of light emitting diodes (LEDs) on the build-up structure and connected with the pixel wiring; and
a cover layer over the emission layer, wherein the cover layer is not directly over a contact ledge of the build-up structure;
wherein the contact ledge spans directly over a portion of the seal ring including an outer perimeter wall adjacent a perimeter edge of the semiconductor substrate and an inner setback wall that is shifted internally from the perimeter edge relative to the outer perimeter wall.