| CPC H10H 20/813 (2025.01) [H10H 20/01 (2025.01); H10H 20/0137 (2025.01); H10H 20/812 (2025.01); H10H 20/821 (2025.01)] | 8 Claims |

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1. A semiconductor device comprising:
a first n-type semiconductor layer;
a tunnel junction layer formed on the first n-type semiconductor layer;
a second p-type semiconductor layer formed on the tunnel junction layer;
a dielectric mask formed on the second p-type semiconductor layer;
a plurality of openings formed on the dielectric mask as holes having a depth reaching the second p-type semiconductor layer; and
a plurality of p-type columnar semiconductor formed on the second p-type semiconductor layer of the openings,
wherein a mesa is further formed, and the tunnel junction layer and the second p-type semiconductor layer are exposed on a side surface of the mesa, further comprising:
a buried layer comprising an n-type semiconductor for filling in a space between the plurality of p-type columnar semiconductors, and
wherein the mesa is a trench for separating elements.
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