US 12,439,729 B2
Heterojunction solar cell and manufacturing method thereof
Chaohui Lin, Quanzhou (CN); and Kairui Lin, Quanzhou (CN)
Assigned to GOLD STONE (FUJIAN) ENERGY COMPANY LIMITED, Quanzhou (CN)
Filed by Gold Stone (Fujian) Energy Company Limited, Quanzhou (CN)
Filed on Sep. 1, 2023, as Appl. No. 18/241,288.
Claims priority of application No. 202211066022.9 (CN), filed on Sep. 1, 2022; and application No. 202211209200.9 (CN), filed on Sep. 30, 2022.
Prior Publication US 2024/0079505 A1, Mar. 7, 2024
Int. Cl. H10F 77/30 (2025.01); H10F 10/17 (2025.01); H10F 71/00 (2025.01)
CPC H10F 77/311 (2025.01) [H10F 10/17 (2025.01); H10F 71/1221 (2025.01)] 20 Claims
OG exemplary drawing
 
1. A manufacturing method of a heterojunction solar cell, wherein the heterojunction solar cell comprises a first electrode, a first conductive film layer, an N-type semiconductor film layer, an intrinsic film layer, a semiconductor substrate, a tunnel oxide layer, a P-type carbon-doped semiconductor film layer, a concentrated P-type doped semiconductor film layer, a second conductive film layer, and a second electrode sequentially stacked from a light-facing surface to a backlight surface, wherein the first conductive film layer completely covers the N-type semiconductor film layer; the first electrode is electrically connected to the N-type semiconductor film layer through the first conductive film layer; the second conductive film layer completely covers the concentrated P-type doped semiconductor film layer; and the second electrode is electrically connected to the concentrated P-type doped semiconductor film layer through the second conductive film layer, wherein the second conductive film layer comprises a transparent conductive film layer, a metal conductive layer, and a protective layer, wherein the transparent conductive film layer has a thickness of 20-100 nm, and the metal conductive layer is made of copper, with a thickness of 100-500 nm, and the protective layer is made of a metal nickel-chromium alloy with a thickness of 30-100 nm, wherein the method comprises the following steps:
A: forming a tunnel oxide layer on a first main surface of a semiconductor substrate;
B: forming a first intrinsic polysilicon layer on the tunnel oxide layer;
C: forming the first intrinsic polysilicon layer into a P-type polysilicon layer by diffusion annealing;
D: removing a borosilicate glass (BSG) layer formed by the diffusion annealing;
E: forming a mask layer on the P-type polysilicon layer;
F: performing texturing and cleaning on a second main surface of the semiconductor substrate, and removing the mask layer;
G: forming a second intrinsic amorphous silicon layer on the second main surface of the semiconductor substrate; and
H: forming an N-type oxygen-doped microcrystalline silicon layer on the second intrinsic amorphous silicon layer.