US 12,439,726 B2
Solar cell and manufacturing method therefor
Xiulin Jiang, Yangzhou (CN); Bin Chen, Yangzhou (CN); and Wei Shan, Yangzhou (CN)
Assigned to JA Solar Technology Yangzhou Co., LTD., Yangzhou (CN)
Appl. No. 18/703,157
Filed by JA SOLAR TECHNOLOGY YANGZHOU CO., LTD., Yangzhou (CN)
PCT Filed Nov. 18, 2021, PCT No. PCT/CN2021/131385
§ 371(c)(1), (2) Date Apr. 19, 2024,
PCT Pub. No. WO2023/065448, PCT Pub. Date Apr. 27, 2023.
Claims priority of application No. 202111219711.4 (CN), filed on Oct. 20, 2021.
Prior Publication US 2025/0228035 A1, Jul. 10, 2025
Int. Cl. H01L 31/044 (2014.01); H10F 71/00 (2025.01); H10F 77/164 (2025.01); H10F 77/20 (2025.01); H10F 77/30 (2025.01); H10F 77/70 (2025.01)
CPC H10F 77/215 (2025.01) [H10F 71/1221 (2025.01); H10F 71/129 (2025.01); H10F 77/1642 (2025.01); H10F 77/315 (2025.01); H10F 77/703 (2025.01)] 9 Claims
OG exemplary drawing
 
1. A method for preparing a solar cell, which comprises:
step 101: sequentially forming a tunnel silicon oxide layer, an N-type doped polysilicon layer, and a front metal layer in an entire fashion on a front surface of a P-type silicon substrate;
step 102: subjecting an entire front metal layer to a photoetching process to form a patterned front fine gate electrode,
wherein the step 102 further comprises:
step 2-1: forming a photoresist layer on the front metal layer;
step 2-2: subjecting the photoresist layer to an exposing process by means of a mask, the photoresist layer in an exposed region forming an exposed photoresist layer, and the photoresist layer in an unexposed region being removed using a first solution to expose the front metal layer;
step 2-3: removing the exposed front metal layer using a second solution, the front metal layer covered by the exposed photoresist layer forming the patterned front fine gate electrode; and
step 2-4: removing the exposed photoresist layer using a film stripping solution; and
step 103: subjecting the tunnel silicon oxide layer and the N-type doped polysilicon layer in a region not covered by the front fine gate electrode to chemical etching to form a local tunnel silicon oxide layer and a local N-type doped polysilicon layer,
wherein the width of the local tunnel silicon oxide layer and the width the local N-type doped polysilicon layer are the same as the width of the front fine gate electrode.