US 12,439,721 B2
Solid-state imaging device
Tokihisa Kaneguchi, Kanagawa (JP); and Kan Shimizu, Kanagawa (JP)
Assigned to Sony Semiconductor Solutions Corporation, Kanagawa (JP)
Appl. No. 17/909,822
Filed by SONY SEMICONDUCTOR SOLUTIONS CORPORATION, Kanagawa (JP)
PCT Filed Mar. 17, 2021, PCT No. PCT/JP2021/010737
§ 371(c)(1), (2) Date Sep. 7, 2022,
PCT Pub. No. WO2021/193266, PCT Pub. Date Sep. 30, 2021.
Claims priority of application No. 2020-057974 (JP), filed on Mar. 27, 2020.
Prior Publication US 2023/0103730 A1, Apr. 6, 2023
Int. Cl. H10F 39/00 (2025.01); H10F 39/12 (2025.01)
CPC H10F 39/811 (2025.01) [H10F 39/809 (2025.01); H10F 39/199 (2025.01)] 20 Claims
OG exemplary drawing
 
1. A solid-state imaging device, comprising:
a first substrate including a first semiconductor substrate in which multiple photoelectric conversion sections are formed to be embedded, and a multilayer wiring layer formed on one surface side of the first semiconductor substrate, the multiple photoelectric conversion sections being included in a sensor pixel;
one or multiple second substrates attached to the first substrate with the multilayer wiring layer interposed therebetween;
a first wiring layer provided in the multilayer wiring layer and including multiple first thin metal wires formed at substantially same first pitches;
a second wiring layer stacked above the first wiring layer in the multilayer wiring layer and including multiple second thin metal wires formed between the multiple first thin metal wires at substantially same second pitches in a plan view; and
a first alignment part formed above the second wiring layer in the multilayer wiring layer.