| CPC H10F 39/199 (2025.01) [H10F 39/026 (2025.01); H10F 39/802 (2025.01)] | 20 Claims |

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1. A method for forming an integrated chip, the method comprising:
depositing a base semiconductor layer over a substrate;
depositing a backside semiconductor layer over the base semiconductor layer, wherein the backside semiconductor layer has a first doping type;
forming a diffusion barrier structure over the backside semiconductor layer;
depositing a sensor semiconductor layer over the diffusion barrier structure, wherein the sensor semiconductor layer has the first doping type;
forming a photodetector in the sensor semiconductor layer; and
removing the base semiconductor layer and the substrate from along the backside semiconductor layer,
wherein the sensor semiconductor layer is doped with a first dopant and the backside semiconductor layer is doped with a second dopant, and wherein forming the diffusion barrier structure comprises depositing a plurality of diffusion barrier layers with a plurality of spacer layers arranged therebetween in an alternating fashion, the plurality of diffusion barrier layers comprising a semiconductor doped with a third dopant different from the first dopant and the second dopant.
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