| CPC H10D 88/00 (2025.01) [H10B 12/03 (2023.02); H10B 12/05 (2023.02); H10D 1/692 (2025.01); H10D 30/6728 (2025.01); H10D 30/6755 (2025.01); H10B 12/31 (2023.02); H10B 12/33 (2023.02)] | 10 Claims |

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1. A semiconductor memory device comprising:
a first conductive layer;
a second conductive layer;
a first oxide semiconductor layer provided between the first conductive layer and the second conductive layer;
a first gate electrode surrounding the first oxide semiconductor layer;
a first gate insulating film provided between the first oxide semiconductor layer and the first gate electrode;
a first electrode provided in a first direction with respect to the second conductive layer, the first direction being a direction connecting the first conductive layer and the second conductive layer, the second conductive layer provided between the first oxide semiconductor layer and the first electrode, the first electrode electrically connected to the second conductive layer, and the first electrode containing titanium (Ti);
a second electrode surrounding the first electrode and containing the titanium (Ti);
a first capacitor insulating film provided between the first electrode and the second electrode, the first capacitor insulating film including a first region and a second region between the first region and the second electrode, an atomic concentration of the titanium (Ti) of the second region being higher than an atomic concentration of the titanium (Ti) of the first region;
a third conductive layer provided in the first direction with respect to the first conductive layer, the third conductive layer electrically connected to the first conductive layer;
a fourth conductive layer provided in the first direction with respect to the third conductive layer, the third conductive layer provided between the first conductive layer and the fourth conductive layer;
a second oxide semiconductor layer provided between the third conductive layer and the fourth conductive layer;
a second gate electrode surrounding the second oxide semiconductor layer;
a second gate insulating film provided between the second oxide semiconductor layer and the second gate electrode;
a third electrode provided in the first direction with respect to the fourth conductive layer, the fourth conductive layer provided between the second oxide semiconductor layer and the third electrode, the third electrode electrically connected to the fourth conductive layer, and the third electrode containing the titanium (Ti);
a fourth electrode surrounding the third electrode and containing the titanium (Ti); and
a second capacitor insulating film provided between the third electrode and the fourth electrode, the second capacitor insulating film including a third region and a fourth region between the third region and the fourth electrode, an atomic concentration of the titanium (Ti) of the fourth region being higher than an atomic concentration of the titanium (Ti) of the third region.
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