| CPC H10D 86/60 (2025.01) [G09G 3/32 (2013.01); H10D 86/441 (2025.01); G09G 2300/0426 (2013.01); G09G 2300/0809 (2013.01); G09G 2310/0243 (2013.01); G09G 2310/0267 (2013.01); H10H 29/142 (2025.01); H10K 59/1213 (2023.02); H10K 59/1216 (2023.02); H10K 59/131 (2023.02); H10K 59/35 (2023.02)] | 13 Claims |
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1. A display device, comprising:
a substrate;
a polycrystalline semiconductor layer on the substrate, the polycrystalline semiconductor layer including a channel, a first electrode, and a second electrode of a first transistor and a channel, a first electrode, and a second electrode of a second transistor;
a first gate conductor layer including a gate electrode of the first transistor overlapping the channel of the first transistor, and a gate electrode of the second transistor overlapping the channel of the second transistor;
an oxide semiconductor layer on the substrate, the oxide semiconductor layer including a channel, a first electrode, and a second electrode of a third transistor;
a second gate conductor layer including a lower gate electrode of the third transistor overlapping the channel of the third transistor;
a third gate conductor layer including an upper gate electrode of the third transistor overlapping the channel of the third transistor;
a first data conductor layer including a first initialization voltage supply line electrically connected to the second transistor, a second initialization voltage supply line, and a first connection electrode electrically connected to the second electrode of the third transistor and the gate electrode of the first transistor; and
a fourth transistor connected to the second initialization voltage supply line,
wherein the second initialization voltage supply line is disposed on the same layer as the first initialization voltage supply line.
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