| CPC H10D 86/60 (2025.01) [G09G 3/20 (2013.01); H10D 86/441 (2025.01); G09G 2310/0297 (2013.01)] | 18 Claims |
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1. A demultiplexing circuit, comprising:
at least one demultiplexing module, in which each demultiplexing module is electrically connected to an input signal line and a plurality of output signal lines, each demultiplexing module comprises a plurality of demultiplexing units, each of the demultiplexing units comprises a data writing transistor and a compensation unit electrically connected to the data writing transistor, an output end of the data writing transistor is electrically connected to a corresponding output signal line; and
a switch control module, comprising a plurality of switch control units electrically connected to a switch control line, in which each of the switch control units is electrically connected to a clock signal line, each of the switch control units has an output end electrically connected to a control end of the data writing transistor of one of the demultiplexing units,
wherein each of the switch control units is configured to output the clock signal transmitted by the clock signal line to the control end of a corresponding demultiplexing unit according to a switch control signal transmitted by the switch control line, the compensation unit of each of the demultiplexing units is configured to detect a threshold voltage of the data writing transistor and receive a corresponding compensation control signal to compensate for the threshold voltage of the data writing transistor; and
wherein the compensation unit comprises:
a compensation transistor, in which an input end of the compensation transistor is electrically connected to a corresponding input signal line, the output end of the compensation transistor is electrically connected to the input end of the data writing transistor, the control end of the compensation transistor receives the corresponding compensation control signal; and
a first capacitor, in which a first end of the first capacitor is electrically connected to the control end of the data writing transistor, a second end of the first capacitor is electrically connected to the output end of the data writing transistor.
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