US 12,439,692 B2
Display substrate, manufacturing method therefor, and display apparatus
Hui Lu, Beijing (CN); Yipeng Chen, Beijing (CN); Shuai Xie, Beijing (CN); Fei Fang, Beijing (CN); Shuo Li, Beijing (CN); Xuewei Tian, Beijing (CN); and Ling Shi, Beijing (CN)
Assigned to Chengdu BOE Optoelectronics Technology Co., Ltd., Sichuan (CN); and BOE Technology Group Co., Ltd., Beijing (CN)
Appl. No. 17/795,887
Filed by Chengdu BOE Optoelectronics Technology Co., Ltd., Sichuan (CN); and BOE Technology Group Co., Ltd., Beijing (CN)
PCT Filed Sep. 18, 2021, PCT No. PCT/CN2021/119351
§ 371(c)(1), (2) Date Jul. 28, 2022,
PCT Pub. No. WO2023/039886, PCT Pub. Date Mar. 23, 2023.
Prior Publication US 2024/0297173 A1, Sep. 5, 2024
Int. Cl. H10D 86/60 (2025.01); G09G 3/3233 (2016.01); H10D 86/01 (2025.01); H10D 86/40 (2025.01); H10K 59/131 (2023.01)
CPC H10D 86/60 (2025.01) [G09G 3/3233 (2013.01); H10D 86/0221 (2025.01); H10D 86/423 (2025.01); H10D 86/441 (2025.01); H10K 59/131 (2023.02); G09G 2300/0426 (2013.01); G09G 2300/0465 (2013.01); G09G 2300/0819 (2013.01); G09G 2300/0842 (2013.01); G09G 2300/0861 (2013.01); G09G 2310/08 (2013.01); G09G 2320/0233 (2013.01); G09G 2320/0247 (2013.01); G09G 2330/021 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A display substrate, wherein:
in a direction perpendicular to the display substrate, the display substrate comprises a first semiconductor layer, a first conductive layer, a second conductive layer, a second semiconductor layer, a third conductive layer, a fourth conductive layer, and a fifth conductive layer that are sequentially disposed on a substrate;
the first semiconductor layer comprises active layers of a plurality of poly silicon transistors, the first conductive layer comprises gates of the plurality of poly silicon transistors, a first electrode plate of a storage capacitor and a first scan signal line, the second conductive layer comprises a second electrode plate of the storage capacitor, the second semiconductor layer comprises active layers of a plurality of oxide transistors, the third conductive layer comprises gates of the plurality of oxide transistors, the fourth conductive layer comprises first electrodes and second electrodes of the plurality of poly silicon transistors, and first electrodes and second electrodes of the plurality of oxide transistors, and the fifth conductive layer comprises a first power supply line and a data signal line;
in a direction parallel to the display substrate, the display substrate comprises a plurality of sub-pixels, and any two adjacent rows of sub-pixels are symmetrical in an extension direction of the first scan signal line; and
first power supply lines in two adjacent columns of sub-pixels are connected with each other to form an integrated structure.