US 12,439,684 B2
Three-dimensional semiconductor device and method of fabricating the same
Donghoon Hwang, Suwon-si (KR); Myungil Kang, Suwon-si (KR); Minchan Gwak, Suwon-si (KR); Kyungho Kim, Suwon-si (KR); Kyung Hee Cho, Suwon-si (KR); and Doyoung Choi, Suwon-si (KR)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed by SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed on May 12, 2023, as Appl. No. 18/196,741.
Claims priority of application No. 10-2022-0123341 (KR), filed on Sep. 28, 2022.
Prior Publication US 2024/0105724 A1, Mar. 28, 2024
Int. Cl. H10D 84/85 (2025.01); H10D 30/01 (2025.01); H10D 30/43 (2025.01); H10D 30/67 (2025.01); H10D 62/10 (2025.01); H10D 64/01 (2025.01); H10D 84/01 (2025.01); H10D 84/03 (2025.01); H10D 88/00 (2025.01)
CPC H10D 84/856 (2025.01) [H10D 30/014 (2025.01); H10D 30/43 (2025.01); H10D 30/6729 (2025.01); H10D 30/6735 (2025.01); H10D 62/121 (2025.01); H10D 64/017 (2025.01); H10D 84/0167 (2025.01); H10D 84/017 (2025.01); H10D 84/0186 (2025.01); H10D 84/038 (2025.01); H10D 88/01 (2025.01)] 20 Claims
OG exemplary drawing
 
1. A three-dimensional semiconductor device, comprising:
a first active region on a substrate, the first active region comprising a lower channel pattern and a lower source/drain pattern connected to the lower channel pattern;
a second active region on the first active region, the second active region comprising an upper channel pattern and an upper source/drain pattern connected to the upper channel pattern;
a gate electrode on the lower channel pattern and the upper channel pattern;
a lower contact electrically connected to the lower source/drain pattern, the lower contact having a bar shape extending on the lower source/drain pattern in a first direction;
a first active contact coupled to the lower contact; and
a second active contact coupled to the upper source/drain pattern,
wherein a first width of the lower source/drain pattern in a second direction is larger than a second width of the lower contact in the second direction.
 
16. A three-dimensional semiconductor device, comprising:
a first active region on a first region of a substrate, the first active region comprising a first lower channel pattern and a first lower source/drain pattern connected to the first lower channel pattern;
a second active region on the first active region, the second active region comprising a first upper channel pattern and a first upper source/drain pattern connected to the first upper channel pattern;
a gate electrode on the first lower channel pattern and the first upper channel pattern;
a first peripheral active region on a second region of the substrate, the first peripheral active region comprising a second lower channel pattern and a second lower source/drain pattern connected to the second lower channel pattern;
a second peripheral active region on the first peripheral active region, the second peripheral active region comprising a second upper channel pattern and a second upper source/drain pattern connected to the second upper channel pattern;
a peripheral gate electrode on the second lower channel pattern and the second upper channel pattern;
a first active contact coupled to the first upper source/drain pattern; and
a second active contact coupled to the second upper source/drain pattern,
wherein the first upper channel pattern comprises a pair of first upper channel patterns, which are adjacent to each other,
wherein the first upper source/drain pattern is provided as a continuous body connecting the pair of first upper channel patterns to each other,
wherein the second upper channel pattern comprises a pair of second upper channel patterns, which are adjacent to each other,
wherein the second upper source/drain pattern comprises a first sub-pattern connected to one of the pair of second upper channel patterns, and a second sub-pattern connected to another one of the pair of second upper channel patterns, and
wherein the first sub-pattern is separated from the second sub-pattern.