| CPC H10D 84/811 (2025.01) [H10D 64/513 (2025.01); H10D 89/611 (2025.01)] | 10 Claims |
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1. A semiconductor device having a semiconductor chip in which a first field effect transistor and a second field effect transistor for current detection are formed, the semiconductor device comprising:
a semiconductor substrate of a first conductivity type having a first main surface and a second main surface opposite to the first main surface, and having an annular first region and a second region surrounded by the first region in plan view;
a plurality of first trenches formed from the first main surface of the semiconductor substrate to reach an intermediate depth of the semiconductor substrate, extending in a first direction along the first main surface of the semiconductor substrate, and arranged in a second direction orthogonal to the first direction in plan view;
a first semiconductor region of a second conductivity type different from the first conductivity type formed in the semiconductor substrate so as to be in contact with side surfaces of the first trenches;
a source region of the first conductivity type in contact with each side surface of the plurality of first trenches, the first main surface of the semiconductor substrate, and the first semiconductor region;
a drain region of the first conductivity type formed in the semiconductor substrate including the second main surface of the semiconductor substrate;
a gate electrode and a first electrode formed inside each of the plurality of first trenches via a first insulating film and insulated from each other; and
a first wiring, a second wiring, and a source pad formed on the semiconductor substrate via an interlayer insulating film,
wherein the gate electrode, the source region, the drain region, and the first semiconductor region of the first region constitute the first field effect transistor,
wherein the gate electrode, the source region, the drain region, and the first semiconductor region of the second region constitute the second field effect transistor,
wherein the source region of the first field effect transistor and the first electrode in the first trench separated from the second region in plan view are electrically connected to the source pad, and
wherein, in plan view, the source region of the second field effect transistor is electrically connected to the second wiring located outside the source pad via the first wiring surrounded by the source pad and the first electrode in the first trench extending over the second region, the first region, and outside of the first region.
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