| CPC H10D 84/038 (2025.01) [H01L 21/02603 (2013.01); H01L 21/31111 (2013.01); H10D 30/0215 (2025.01); H10D 30/031 (2025.01); H10D 30/6713 (2025.01); H10D 30/6729 (2025.01); H10D 30/6735 (2025.01); H10D 30/6757 (2025.01); H10D 30/6758 (2025.01); H10D 62/021 (2025.01); H10D 62/115 (2025.01); H10D 62/121 (2025.01); H10D 64/017 (2025.01); H10D 84/0167 (2025.01); H10D 84/017 (2025.01); H10D 84/0186 (2025.01); H10D 84/0188 (2025.01); H10D 84/85 (2025.01)] | 20 Claims |

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1. A method of fabricating a semiconductor device, comprising:
forming a first dielectric-filled trench within a first part of a dummy gate, wherein the first dielectric-filled trench interposes first and second device regions and contacts respective first and second hybrid fins disposed between the dielectric-filled trench and each of the first and second device regions; and
forming a metal layer within a second part of the dummy gate;
wherein top surfaces of the first and second hybrid fins are substantially level with each other and extend above a top surface of the metal layer.
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