US 12,439,679 B2
FUSI gated device formation
Yi-Huan Chen, Hsin Chu (TW); Chien-Chih Chou, New Taipei (TW); Ta-Wei Lin, Minxiong Township (TW); Hsiao-Chin Tuan, Taowan (TW); Alexander Kalnitsky, San Francisco, CA (US); Kong-Beng Thei, Pao-Shan Village (TW); and Chia-Hong Wu, Taichung (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu (TW)
Filed on Aug. 2, 2023, as Appl. No. 18/363,881.
Application 17/406,276 is a division of application No. 16/169,220, filed on Oct. 24, 2018, granted, now 11,133,226, issued on Sep. 28, 2021.
Application 18/363,881 is a continuation of application No. 17/406,276, filed on Aug. 19, 2021, granted, now 11,823,959.
Claims priority of provisional application 62/748,709, filed on Oct. 22, 2018.
Prior Publication US 2023/0377992 A1, Nov. 23, 2023
Int. Cl. H10D 84/03 (2025.01); H01L 21/28 (2025.01); H01L 21/3105 (2006.01); H01L 21/3213 (2006.01); H10D 30/01 (2025.01); H10D 62/13 (2025.01); H10D 64/27 (2025.01); H10D 64/62 (2025.01); H10D 64/66 (2025.01); H10D 64/68 (2025.01); H10D 84/01 (2025.01); H10D 84/85 (2025.01)
CPC H10D 84/038 (2025.01) [H01L 21/28088 (2013.01); H01L 21/31053 (2013.01); H01L 21/32133 (2013.01); H01L 21/32139 (2013.01); H10D 30/0212 (2025.01); H10D 30/0215 (2025.01); H10D 62/151 (2025.01); H10D 64/517 (2025.01); H10D 64/62 (2025.01); H10D 64/667 (2025.01); H10D 64/685 (2025.01); H10D 84/017 (2025.01); H10D 84/0174 (2025.01); H10D 84/0186 (2025.01); H10D 84/85 (2025.01); H10D 64/514 (2025.01); H10D 64/691 (2025.01)] 20 Claims
OG exemplary drawing
 
1. A method for forming an integrated chip, comprising:
forming a stack of gate layers over a substrate, wherein the stack of gate layers comprises a first dielectric layer on the substrate, a conductive layer on the first dielectric layer, and a polysilicon layer on the conductive layer;
forming a pair of source/drain regions on opposing sides of a central region of the polysilicon layer; and
converting the central region of the polysilicon layer to a first silicide layer, wherein the first silicide layer is spaced between inner sidewalls of the polysilicon layer, wherein the inner sidewalls of the polysilicon layer comprise a first sidewall, wherein a lower vertical segment of the first sidewall physically contacts the first silicide layer, wherein an upper slanted segment of the first sidewall is vertically above a top surface of the first silicide layer, wherein the upper slanted segment of the first sidewall contacts and continuously extends from the lower vertical segment of the first sidewall to an upper surface of the polysilicon layer.