US 12,439,678 B2
Isolation structures
Kai-Hsuan Lee, Hsinchu (TW); Shih-Che Lin, Hsinchu (TW); Po-Yu Huang, Hsinchu (TW); Shih-Chieh Wu, Hsinchu (TW); I-Wen Wu, Hsinchu (TW); Chen-Ming Lee, Taoyuan County (TW); Fu-Kai Yang, Hsinchu (TW); and Mei-Yun Wang, Hsin-Chu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Aug. 13, 2021, as Appl. No. 17/402,079.
Prior Publication US 2023/0048829 A1, Feb. 16, 2023
Int. Cl. H10D 84/03 (2025.01); H01L 21/02 (2006.01); H01L 21/764 (2006.01); H10D 30/01 (2025.01); H10D 30/67 (2025.01); H10D 62/10 (2025.01); H10D 64/01 (2025.01); H10D 84/01 (2025.01); H10D 84/85 (2025.01)
CPC H10D 84/038 (2025.01) [H01L 21/0259 (2013.01); H01L 21/764 (2013.01); H10D 30/031 (2025.01); H10D 30/6713 (2025.01); H10D 30/6735 (2025.01); H10D 30/6757 (2025.01); H10D 62/118 (2025.01); H10D 64/017 (2025.01); H10D 84/0167 (2025.01); H10D 84/017 (2025.01); H10D 84/0188 (2025.01); H10D 84/85 (2025.01)] 20 Claims
OG exemplary drawing
 
1. A method, comprising:
receiving a workpiece comprising:
a fin-shaped structure protruding from a substrate and comprising a first channel region and a second channel region,
a first dummy gate structure disposed over the first channel region and a second dummy gate structure disposed over the second channel region, and
a source/drain feature disposed between the first channel region and the second channel region;
removing a portion of the first dummy gate structure to form a first trench exposing the first channel region;
removing a portion of the first channel region exposed by the first trench and a portion of the substrate directly under the first channel region to extend the first trench;
forming a dielectric feature in the extended first trench, wherein the dielectric feature is spaced apart from the source/drain feature by an air gap; and
after the forming of the dielectric feature, replacing the second dummy gate structure with a gate stack.
 
10. A method, comprising:
receiving a workpiece comprising:
a first active region and a second active region extending from a substrate,
a first isolation feature disposed over the substrate and between the first and the second active regions,
a second isolation feature disposed on the first isolation feature, and
a dummy gate structure comprising a first portion over the first active region and a second portion over the second active region;
removing the first portion of the dummy gate structure and portions of the first active region and the substrate under the first portion of the dummy gate structure to form a trench;
forming a dielectric feature in the trench, wherein the dielectric feature is spaced apart from the second isolation feature by an air gap; and
replacing the second portion of the dummy gate structure with a gate stack.
 
17. A method, comprising:
receiving a semiconductor structure comprising:
a channel region directly over a portion of a substrate,
a dummy gate structure directly over the channel region, and
a source/drain feature over the substrate and electrically coupled to the channel region;
removing the dummy gate structure, the channel region, and the portion of the substrate disposed directly under the channel region to form a trench;
forming a dielectric feature in the trench, wherein the dielectric feature is spaced apart from the source/drain feature and the substrate by an air gap, wherein the air gap extends into the substrate.