US 12,439,677 B2
Method for manufacturing semiconductor device, and semiconductor device
Kejun Mu, Hefei (CN)
Assigned to CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed by CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed on Jul. 19, 2022, as Appl. No. 17/867,835.
Application 17/867,835 is a continuation of application No. PCT/CN2021/128320, filed on Nov. 3, 2021.
Claims priority of application No. 202110937661.7 (CN), filed on Aug. 16, 2021.
Prior Publication US 2023/0049320 A1, Feb. 16, 2023
Int. Cl. H10D 64/27 (2025.01); H01L 21/02 (2006.01); H01L 21/311 (2006.01); H10D 64/01 (2025.01); H10D 64/66 (2025.01)
CPC H10D 64/514 (2025.01) [H01L 21/02236 (2013.01); H01L 21/31111 (2013.01); H10D 64/01 (2025.01); H10D 64/661 (2025.01)] 4 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
a substrate;
a gate insulating layer located on the substrate, and comprising a first end and
a second end opposite to each other in a direction parallel to a channel length; and
a gate layer located on the gate insulating layer, and comprising a first end and a second end opposite to each other in a direction parallel to the channel length; wherein the first end of the gate insulating layer is recessed inwards by a preset length relative to the first end of the gate layer, and the second end of the gate insulating layer is recessed inwards by the preset length relative to the second end of the gate layer;
wherein the first end and the second end of the gate layer each comprise an oxidation layer formed in a reoxidation process, and the oxidation layer does not cover the gate insulating layer;
wherein a thickness of the oxidation layer in the direction parallel to the channel length is equal to the preset length.