US 12,439,668 B2
Field plate and isolation structure for high voltage device
Kaochao Chen, Hsinchu (TW); Chia-Cheng Ho, Hsinchu (TW); and Ming Chyi Liu, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu (TW)
Filed on Jun. 30, 2022, as Appl. No. 17/854,884.
Application 17/854,884 is a continuation of application No. 16/821,247, filed on Mar. 17, 2020, granted, now 11,411,086.
Prior Publication US 2022/0336593 A1, Oct. 20, 2022
Int. Cl. H01L 29/40 (2006.01); H01L 21/3105 (2006.01); H01L 21/768 (2006.01); H10D 30/65 (2025.01); H10D 62/10 (2025.01); H10D 62/832 (2025.01); H10D 64/00 (2025.01)
CPC H10D 64/111 (2025.01) [H01L 21/31053 (2013.01); H01L 21/76829 (2013.01); H10D 30/65 (2025.01); H10D 62/116 (2025.01); H10D 62/8325 (2025.01)] 20 Claims
OG exemplary drawing
 
1. An integrated chip, comprising:
a gate structure overlying a substrate between a source region and a drain region;
a field plate disposed within a first dielectric layer overlying the substrate, wherein the field plate is laterally offset from the gate structure by a non-zero distance in a direction towards the drain region; and
an isolation structure disposed within the substrate, wherein the field plate directly overlies at least a portion of the isolation structure, wherein a distance between outer opposing sidewalls of the field plate is greater than a width of the isolation structure.