US 12,439,667 B2
Method of manufacturing semiconductor device using single slurry chemical mechanical polishing (CMP) process
Joongsuk Oh, Hwaseong-si (KR); Jaeung Koo, Seoul (KR); Boun Yoon, Seoul (KR); Ilyoung Yoon, Hwaseong-si (KR); Kangchun Lee, Suwon-si (KR); Seungjae Lee, Seoul (KR); Junhwan Yim, Seoul (KR); and Huiteak Hong, Yongin-si (KR)
Assigned to Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on Sep. 7, 2022, as Appl. No. 17/930,145.
Claims priority of application No. 10-2022-0002353 (KR), filed on Jan. 6, 2022.
Prior Publication US 2023/0215926 A1, Jul. 6, 2023
Int. Cl. H01L 29/40 (2006.01); H01L 21/3105 (2006.01); H01L 21/321 (2006.01); H01L 29/66 (2006.01); H10D 30/01 (2025.01); H10D 64/01 (2025.01); H10D 30/43 (2025.01); H10D 30/67 (2025.01)
CPC H10D 64/01 (2025.01) [H01L 21/31053 (2013.01); H01L 21/3212 (2013.01); H10D 30/014 (2025.01); H10D 30/031 (2025.01); H10D 30/43 (2025.01); H10D 30/6735 (2025.01)] 17 Claims
OG exemplary drawing
 
1. A method of manufacturing a semiconductor device using a single slurry chemical mechanical polishing (CMP) process, the method comprising:
forming, on a substrate, dummy gate structures extending away from the substrate in a first direction and spaced apart from each other in a second direction perpendicular to the first direction, each dummy gate structure comprising a dummy gate and a mask pattern on an upper surface of the dummy gate;
forming an interlayer insulating layer covering the dummy gate structures; and
performing the single slurry CMP process of removing upper portions of the interlayer insulating layer and the dummy gate structures through the single slurry CMP process, thereby exposing the upper surface of the dummy gate,
wherein, before the performing of the single slurry CMP process, a maximum thickness of the mask pattern is equal to or less than 85 nm, and
in the performing of the single slurry CMP process, one type of slurry composition in which a selectivity of the mask pattern to the interlayer insulating layer is 1 to 2, and a selectivity of the interlayer insulating layer or the mask pattern to the dummy gate is equal to or greater than 50 is used, wherein the performing of the single slurry CMP process comprises:
performing a first process of removing an upper portion of the interlayer insulating layer in a first chamber among three chambers;
performing a second process of exposing an upper surface of the mask pattern having the maximum thickness in a second chamber among the three chambers; and
performing a third process of exposing the upper surface of the dummy gate in a third chamber among the three chambers, wherein the single slurry composition is used in the first process, the second process, and the third process.