| CPC H10D 62/299 (2025.01) [H10D 30/027 (2025.01); H10D 30/65 (2025.01); H10D 62/126 (2025.01); H10D 62/307 (2025.01); H10D 84/0156 (2025.01); H10D 84/038 (2025.01); H01L 21/22 (2013.01); H01L 21/26513 (2013.01); H01L 21/266 (2013.01)] | 20 Claims |
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1. A method of forming a semiconductor device, comprising:
forming a well region within a semiconductor substrate;
the well region formed with a plurality of first regions that abut and alternate with a plurality of second regions, wherein the plurality of first regions are formed with a first doping and the plurality of second regions are formed with a second doping that is different from the first doping, and wherein from a top view;
the plurality of first regions and the plurality of second regions extend continuously in parallel with one another from a first end to a second end of a width of the well region in a first direction; and
the plurality of second regions alternate with and are laterally separated by the plurality of first regions in a second direction perpendicular to the first direction;
forming a gate stack on the plurality of first regions and the plurality of second regions; and
forming a first source/drain region on a top surface of the plurality of first and second regions, wherein the first source/drain region is formed extending from a uniform edge of the well region that spans the width of the well region and is common with an edge of one of the plurality of first regions or one of the plurality of second regions that spans the width of the well region, and the uniform edge is common with an edge of the gate stack, and the plurality of first regions alternate with the plurality of second regions in the second direction that is perpendicular to the uniform edge.
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