| CPC H10D 62/151 (2025.01) [H10D 30/027 (2025.01); H10D 62/834 (2025.01); H10D 84/834 (2025.01); H10D 86/01 (2025.01); H10D 86/201 (2025.01); H01L 21/02532 (2013.01); H01L 21/02576 (2013.01); H01L 21/02639 (2013.01); H10D 64/259 (2025.01)] | 20 Claims |
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1. An integrated chip, comprising:
a semiconductor substrate; and
a first transistor on the semiconductor substrate and comprising a first gate structure over the semiconductor substrate, a first pair of source/drain regions on opposing sides of the first gate structure, and a pair of diffusion barrier structures between the first pair of source/drain regions and a lower region of the semiconductor substrate, wherein the first pair of source/drain regions comprise a first dopant, wherein the diffusion barrier structures are co-doped with the first dopant and a second dopant different from the first dopant, wherein a doping concentration of the first dopant within the first pair of source/drain regions is greater than a doping concentration of the first dopant within the diffusion barrier structures, wherein a doping concentration of the second dopant in the diffusion barrier structures continuously changes from upper surfaces of the diffusion barrier structures in a direction away from the first pair of source/drain regions.
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