US 12,439,660 B2
Vertical transistor with reduced cell height
Brent A. Anderson, Jericho, VT (US); Ruilong Xie, Niskayuna, NY (US); Albert M. Chu, Nashua, NH (US); Hemanth Jagannathan, Niskayuna, NY (US); and Junli Wang, Slingerlands, NY (US)
Assigned to International Business Machines Corporation, Armonk, NY (US)
Filed by INTERNATIONAL BUSINESS MACHINES CORPORATION, Armonk, NY (US)
Filed on Dec. 1, 2022, as Appl. No. 18/060,603.
Prior Publication US 2024/0186375 A1, Jun. 6, 2024
Int. Cl. H10D 62/10 (2025.01); H01L 23/528 (2006.01); H10D 30/62 (2025.01); H10D 30/63 (2025.01); H10D 64/27 (2025.01); H10D 84/85 (2025.01)
CPC H10D 62/127 (2025.01) [H01L 23/5283 (2013.01); H10D 30/6211 (2025.01); H10D 30/63 (2025.01); H10D 64/512 (2025.01); H10D 84/853 (2025.01)] 16 Claims
OG exemplary drawing
 
1. A semiconductor structure comprising:
a vertical semiconductor channel region;
a bottom source drain region arranged on a substrate at a bottom of the vertical semiconductor channel region;
a metal gate disposed around the vertical semiconductor channel region, wherein a first portion of the metal gate is above the vertical semiconductor channel region; and
a gate contact entirely above the vertical semiconductor channel region, wherein a portion of the gate contact is directly above a portion of the vertical semiconductor channel region.