US 12,439,659 B2
Gate-all-around integrated circuit structures having germanium-diffused nanoribbon channel structures
Andy Chih-Hung Wei, Yamhill, OR (US); Guillaume Bouche, Hillsboro, OR (US); and Jack T. Kavalieros, Portland, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Dec. 22, 2020, as Appl. No. 17/131,622.
Prior Publication US 2022/0199774 A1, Jun. 23, 2022
Int. Cl. H01L 29/06 (2006.01); H01L 27/088 (2006.01); H01L 29/78 (2006.01); H10D 30/62 (2025.01); H10D 30/69 (2025.01); H10D 62/10 (2025.01); H10D 84/83 (2025.01)
CPC H10D 62/121 (2025.01) [H10D 30/6211 (2025.01); H10D 30/797 (2025.01); H10D 84/834 (2025.01)] 20 Claims
OG exemplary drawing
 
1. An integrated circuit structure, comprising:
a vertical arrangement of nanowires above a sub-fin structure, wherein individual ones of the vertical arrangement of nanowires comprise silicon and germanium, and wherein the sub-fin structure has a relatively higher germanium concentration at a top of the sub-fin structure than at a bottom of the sub-fin structure;
an isolation structure laterally adjacent to the sub-fin structure, the isolation structure having a top surface below the top of the sub-fin structure; and
a gate stack over the vertical arrangement of nanowires, the gate stack intervening between individual ones of the vertical arrangement of nanowires, the gate stack having a bottommost surface below the top of the sub-fin structure, and the gate stack laterally adjacent to a portion of the sub-fin structure having a lower germanium concentration than the top of the sub-fin structure.