US 12,439,658 B2
Semiconductor device including a superlattice providing metal work function tuning
Robert J. Mears, Wellesley, MA (US); and Hideki Takeuchi, San Jose, CA (US)
Assigned to ATOMERA INCORPORATED, Los Gatos, CA (US)
Filed by ATOMERA INCORPORATED, Los Gatos, CA (US)
Filed on May 18, 2022, as Appl. No. 17/663,852.
Claims priority of provisional application 63/212,292, filed on Jun. 18, 2021.
Claims priority of provisional application 63/211,174, filed on Jun. 16, 2021.
Claims priority of provisional application 63/189,909, filed on May 18, 2021.
Prior Publication US 2022/0376047 A1, Nov. 24, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. H10D 30/01 (2025.01); H10D 30/67 (2025.01); H10D 30/69 (2025.01); H10D 62/10 (2025.01); H10D 62/815 (2025.01); H10D 84/01 (2025.01); H10D 84/03 (2025.01)
CPC H10D 62/118 (2025.01) [H10D 30/031 (2025.01); H10D 30/6713 (2025.01); H10D 30/6735 (2025.01); H10D 30/6757 (2025.01); H10D 30/751 (2025.01); H10D 30/791 (2025.01); H10D 62/815 (2025.01); H10D 62/8171 (2025.01); H10D 84/0128 (2025.01); H10D 84/013 (2025.01); H10D 84/038 (2025.01)] 21 Claims
OG exemplary drawing
 
1. A semiconductor gate-all-around (GAA) device comprising:
a semiconductor substrate;
source and drain regions on the semiconductor substrate;
a plurality of semiconductor nanostructures extending between the source and drain regions;
a gate surrounding the plurality of semiconductor nanostructures in a gate-all-around arrangement; and
a dopant diffusion liner adjacent at least one of the source and drain regions and comprising a first superlattice, the first superlattice comprising a plurality of stacked groups of layers, each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.