| CPC H10D 62/115 (2025.01) [H10D 30/024 (2025.01); H10D 30/62 (2025.01); H10D 30/6743 (2025.01)] | 20 Claims |
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1. A device comprising:
a semiconductor substrate;
isolation regions over a bulk portion of the semiconductor substrate;
a semiconductor strip between opposite portions of the isolation regions;
a dielectric region comprising:
a first dielectric layer having a U-shaped cross-sectional view; and
a second dielectric layer comprising:
a first portion in the first dielectric layer; and
a second portion over the first dielectric layer and the first portion of the dielectric region;
a semiconductor region over and contacting the semiconductor strip, wherein the semiconductor region extends laterally beyond edges of the semiconductor strip to contact the second portion of the second dielectric layer;
a semiconductor fin overlapping a portion of the semiconductor strip, wherein a first top surface of the semiconductor fin is coplanar with a second top surface of the second portion of the second dielectric layer; and
a gate stack on the semiconductor fin, wherein the gate stack comprises a portion between the semiconductor fin and the second portion of the second dielectric layer.
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