US 12,439,655 B2
Semiconductor device with voltage resistant structure
Yuki Nakano, Kyoto (JP); and Ryota Nakamura, Kyoto (JP)
Assigned to ROHM CO., LTD., Kyoto (JP)
Filed by ROHM CO., LTD., Kyoto (JP)
Filed on Dec. 27, 2023, as Appl. No. 18/396,753.
Application 18/396,753 is a continuation of application No. 17/575,148, filed on Jan. 13, 2022, granted, now 11,929,394.
Application 17/575,148 is a continuation of application No. 17/016,006, filed on Sep. 9, 2020, granted, now 11,257,901, issued on Feb. 22, 2022.
Application 17/016,006 is a continuation of application No. 16/723,622, filed on Dec. 20, 2019, granted, now 10,804,356, issued on Oct. 13, 2020.
Application 16/723,622 is a continuation of application No. 15/873,686, filed on Jan. 17, 2018, granted, now 10,546,921, issued on Jan. 28, 2020.
Application 15/873,686 is a continuation of application No. 15/412,785, filed on Jan. 23, 2017, granted, now 9,905,635, issued on Feb. 27, 2018.
Application 15/412,785 is a continuation of application No. 14/771,457, granted, now 9,590,061, issued on Mar. 7, 2017, previously published as PCT/JP2014/055520, filed on Mar. 4, 2014.
Claims priority of application No. 2013-043406 (JP), filed on Mar. 5, 2013.
Prior Publication US 2024/0128315 A1, Apr. 18, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. H10D 62/10 (2025.01); H10D 30/65 (2025.01); H10D 30/66 (2025.01); H10D 62/17 (2025.01); H10D 62/60 (2025.01); H10D 62/83 (2025.01); H10D 62/832 (2025.01); H10D 62/85 (2025.01); H10D 64/00 (2025.01); H10D 64/23 (2025.01); H10D 64/27 (2025.01); H10D 64/66 (2025.01); H10D 64/68 (2025.01)
CPC H10D 62/109 (2025.01) [H10D 30/658 (2025.01); H10D 30/663 (2025.01); H10D 30/665 (2025.01); H10D 30/668 (2025.01); H10D 62/104 (2025.01); H10D 62/106 (2025.01); H10D 62/117 (2025.01); H10D 62/126 (2025.01); H10D 62/127 (2025.01); H10D 62/60 (2025.01); H10D 62/8303 (2025.01); H10D 62/8325 (2025.01); H10D 62/8503 (2025.01); H10D 64/117 (2025.01); H10D 64/252 (2025.01); H10D 64/513 (2025.01); H10D 64/519 (2025.01); H10D 64/662 (2025.01); H10D 64/681 (2025.01); H10D 64/691 (2025.01); H10D 64/693 (2025.01); H10D 62/115 (2025.01); H10D 62/393 (2025.01); H10D 64/256 (2025.01); H10D 64/517 (2025.01); H10D 64/518 (2025.01)] 19 Claims
OG exemplary drawing
 
1. A wide band gap semiconductor device comprising:
a semiconductor substrate;
a first gate insulating film on the semiconductor substrate;
a first gate electrode on the first gate insulating film;
a second gate insulating film on the semiconductor substrate;
a second gate electrode on the second gate insulating film;
a surface insulating film formed over the first gate electrode and the second gate electrode; and
a source electrode over the semiconductor substrate and at least placed over the first gate electrode and the second gate electrode, an outermost portion of the source electrode including an inclined surface in a cross section,
wherein a first portion of a surface of the semiconductor substrate between a center of the first gate electrode and a center of the second gate electrode is recessed compared to a second portion under the center of the first gate electrode and a third portion under the center of the second gate electrode,
the peripheral portion of the semiconductor substrate is recessed and reaches to an edge of the semiconductor substrate, and
a first thickness of at least part of the surface insulating film under the source electrode is thinner than a second thickness of at least part of the surface insulating film formed in an area other than under the source electrode when viewed in a cross section.