US 12,439,654 B2
Semiconductor device
Tomoko Matsudai, Tokyo (JP); and Yoko Iwakaji, Tokyo (JP)
Assigned to Kabushiki Kaisha Toshiba, Tokyo (JP); and Toshiba Electronic Devices & Storage Corporation, Tokyo (JP)
Filed by Kabushiki Kaisha Toshiba, Tokyo (JP); and Toshiba Electronic Devices & Storage Corporation, Tokyo (JP)
Filed on Apr. 12, 2024, as Appl. No. 18/634,027.
Application 18/634,027 is a division of application No. 17/472,166, filed on Sep. 10, 2021, granted, now 11,984,473.
Claims priority of application No. 2021-044115 (JP), filed on Mar. 17, 2021.
Prior Publication US 2024/0274656 A1, Aug. 15, 2024
Int. Cl. H10D 62/10 (2025.01); H10D 8/00 (2025.01); H10D 12/00 (2025.01); H10D 84/60 (2025.01)
CPC H10D 62/106 (2025.01) [H10D 8/422 (2025.01); H10D 12/481 (2025.01); H10D 84/617 (2025.01)] 15 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
a transistor region including:
a semiconductor layer having a first face and a second face opposite to the first face;
a first transistor having a first gate electrode provided on a first face side of the semiconductor layer; and
a second transistor having a second gate electrode provided on a second face side of the semiconductor layer; and
an adjacent region adjacent to the transistor region and including:
the semiconductor layer; and
a third transistor having a third gate electrode electrically connected to the second gate electrode and provided on the second face side of the semiconductor layer, and the third transistor having an absolute value of a threshold voltage smaller than an absolute value of a threshold voltage of the second transistor,
wherein p-type impurity concentration in the semiconductor layer of a portion facing the third gate electrode is lower than p-type impurity concentration in the semiconductor layer of a portion facing the second gate electrode.