US 12,439,651 B2
Integrated circuit structure
Wei-Hao Lu, Taoyuan (TW); Chien-I Kuo, Hsinchu County (TW); Li-Li Su, Hsinchu County (TW); Wei-Yang Lee, Taipei (TW); and Yee-Chia Yeo, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed on Jun. 23, 2023, as Appl. No. 18/340,454.
Application 18/340,454 is a division of application No. 17/225,786, filed on Apr. 8, 2021, granted, now 11,688,793.
Prior Publication US 2023/0343855 A1, Oct. 26, 2023
Int. Cl. H10D 88/00 (2025.01); H10D 30/67 (2025.01); H10D 62/00 (2025.01); H10D 64/01 (2025.01); H10D 84/01 (2025.01); H10D 84/03 (2025.01)
CPC H10D 62/021 (2025.01) [H10D 30/6729 (2025.01); H10D 30/6735 (2025.01); H10D 30/6757 (2025.01); H10D 64/01 (2025.01); H10D 64/017 (2025.01); H10D 84/013 (2025.01); H10D 84/0149 (2025.01); H10D 84/038 (2025.01)] 20 Claims
OG exemplary drawing
 
1. An integrated circuit (IC) structure, comprising:
a dielectric layer;
a semiconductor layer over the dielectric layer;
a gate structure over the dielectric layer and the semiconductor layer;
a first source/drain epitaxial structure and a second source/drain epitaxial structure respectively on opposite sides of the semiconductor layer;
a backside via extending through the dielectric layer to the first source/drain epitaxial structure;
an epitaxial feature between the second source/drain epitaxial structure and the dielectric layer; and
a germanium residue at an interface between the backside via and the dielectric layer, wherein the first and second source/drain epitaxial structures are n-type features.