| CPC H10D 48/362 (2025.01) [H01L 21/02181 (2013.01); H01L 21/0228 (2013.01); H01L 21/02568 (2013.01); H01L 21/47576 (2013.01); H01L 23/3171 (2013.01); H10D 30/6729 (2025.01); H10D 30/6739 (2025.01); H10D 30/6757 (2025.01); H10D 62/80 (2025.01); H10D 64/62 (2025.01); H10D 84/02 (2025.01); H10D 84/85 (2025.01); H10D 99/00 (2025.01); H10K 10/466 (2023.02); H10K 10/484 (2023.02); H10K 10/84 (2023.02); H10K 10/88 (2023.02); H10K 19/10 (2023.02); H10K 85/221 (2023.02)] | 20 Claims |
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1. A method comprising:
forming a first gate electrode and a second gate electrode;
forming a gate dielectric layer extending over the first gate electrode and the second gate electrode;
forming an n-type transistor comprising:
forming a first low-dimensional semiconductor layer over the gate dielectric layer, wherein a first portion of the first low-dimensional semiconductor layer is directly over the first gate electrode;
forming first source/drain contacts on opposing sides of the first gate electrode, wherein one of the first source/drain contacts is in contact with a first part of the first low-dimensional semiconductor layer;
depositing a dielectric doping layer comprising aluminum oxide or hafnium oxide over and contacting the first low-dimensional semiconductor layer; and
forming a p-type transistor comprising:
forming a second low-dimensional semiconductor layer over the gate dielectric layer, wherein a second portion of the second low-dimensional semiconductor layer is directly over the second gate electrode;
forming second source/drain contacts on opposing sides of the second gate electrode, wherein one of the second source/drain contacts is in contact with a second part of the second low-dimensional semiconductor layer; and
depositing a dielectric passivation layer over and contacting the second low-dimensional semiconductor layer, wherein the dielectric passivation layer and the dielectric doping layer are formed of different materials.
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