US 12,439,649 B2
Dislocation enhanced transistor device and method
Toshihiko Miyashita, Boise, ID (US); and Jung Chao Chiou, Boise, ID (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Apr. 14, 2022, as Appl. No. 17/720,990.
Prior Publication US 2023/0335642 A1, Oct. 19, 2023
Int. Cl. H01L 29/10 (2006.01); H10B 12/00 (2023.01); H10D 30/69 (2025.01); H10D 62/17 (2025.01)
CPC H10D 30/791 (2025.01) [H10B 12/05 (2023.02); H10B 12/30 (2023.02); H10D 62/235 (2025.01)] 16 Claims
OG exemplary drawing
 
1. A transistor, comprising:
a source region and a drain region separated by a channel and formed in a (100) surface of a semiconductor substrate wherein the channel is oriented in a <100> direction;
a gate dielectric over the channel;
a gate over the gate dielectric;
one or more strain induced dislocations adjacent to the channel.