US 12,439,648 B2
Transistor gate structures and methods of forming thereof
Hsin-Yi Lee, Hsinchu (TW); Weng Chang, Hsinchu (TW); and Chi On Chui, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Jun. 6, 2022, as Appl. No. 17/833,348.
Claims priority of provisional application 63/362,053, filed on Mar. 29, 2022.
Prior Publication US 2023/0317859 A1, Oct. 5, 2023
Int. Cl. H01L 29/786 (2006.01); H01L 29/06 (2006.01); H01L 29/423 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01); H10D 30/01 (2025.01); H10D 30/62 (2025.01); H10D 30/67 (2025.01); H10D 62/10 (2025.01)
CPC H10D 30/6757 (2025.01) [H10D 30/024 (2025.01); H10D 30/62 (2025.01); H10D 30/6735 (2025.01); H10D 62/119 (2025.01)] 20 Claims
OG exemplary drawing
 
1. A device comprising:
a semiconductor substrate;
a vertically stacked set of nanostructures over the semiconductor substrate;
a first source/drain region;
a second source/drain region, wherein the vertically stacked set of nanostructures extends between the first source/drain region and the second source/drain region along a first cross-section;
a gate structure encasing the vertically stacked set of nanostructures along a second cross-section, wherein the second cross-section is along a longitudinal axis of the gate structure, and wherein the gate structure comprises:
a gate dielectric encasing each of the vertically stacked set of nanostructures;
a first metal carbide layer over the gate dielectric, wherein the first metal carbide layer comprises Ce, Hf, V, Nb, Sc, Y, or Mo;
a second metal carbide layer between the first metal carbide layer and the gate dielectric, wherein the second metal carbide layer comprises a different metal element than the first metal carbide layer; and
a gate fill material over the first metal carbide layer.