US 12,439,645 B2
High electron mobility transistor device and manufacturing method thereof
Jih-Wen Chou, Hsinchu (TW); Hsin-Hong Chen, Hsinchu (TW); Yu-Jen Huang, Hsinchu (TW); Robin Christine Hwang, Taipei (TW); Po-Hsien Yeh, Hsinchu County (TW); and Chih-Hung Lu, Taichung (TW)
Assigned to Powerchip Semiconductor Manufacturing Corporation, Hsinchu (TW)
Filed by Powerchip Semiconductor Manufacturing Corporation, Hsinchu (TW)
Filed on Sep. 12, 2022, as Appl. No. 17/942,189.
Claims priority of application No. 111109980 (TW), filed on Mar. 18, 2022.
Prior Publication US 2023/0299169 A1, Sep. 21, 2023
Int. Cl. H10D 30/67 (2025.01); H01L 21/285 (2006.01); H01L 23/31 (2006.01); H10D 30/01 (2025.01); H10D 30/47 (2025.01); H10D 62/824 (2025.01); H10D 62/85 (2025.01); H10D 64/27 (2025.01); H10D 64/64 (2025.01)
CPC H10D 30/675 (2025.01) [H01L 21/28581 (2013.01); H01L 21/28587 (2013.01); H01L 23/3192 (2013.01); H10D 30/015 (2025.01); H10D 30/475 (2025.01); H10D 30/6738 (2025.01); H10D 62/824 (2025.01); H10D 62/85 (2025.01); H10D 62/8503 (2025.01); H10D 64/411 (2025.01); H10D 64/64 (2025.01)] 20 Claims
OG exemplary drawing
 
1. A high electron mobility transistor (HEMT) device, comprising:
a channel layer;
a first barrier layer disposed on the channel layer;
a gate structure disposed on the first barrier layer and comprising:
a first P-type gallium nitride layer disposed on the first barrier layer;
a second barrier layer disposed on the first P-type gallium nitride layer; and
a second P-type gallium nitride layer disposed on the second barrier layer,
wherein a width of the second P-type gallium nitride layer is smaller than a width of the first P-type gallium nitride layer; and
a spacer disposed on a sidewall of the second P-type gallium nitride layer.