US 12,439,641 B2
Compact 3D design and connections with optimum 3D transistor stacking
H. Jim Fulford, Marianna, FL (US); Mark I. Gardner, Cedar Creek, TX (US); and Partha Mukhopadhyay, Oviedo, FL (US)
Assigned to Tokyo Electron Limited, Tokyo (JP)
Filed by Tokyo Electron Limited, Tokyo (JP)
Filed on Apr. 6, 2022, as Appl. No. 17/714,716.
Claims priority of provisional application 63/281,427, filed on Nov. 19, 2021.
Prior Publication US 2023/0163185 A1, May 25, 2023
Int. Cl. H10D 30/67 (2025.01); H10D 62/10 (2025.01); H10D 64/23 (2025.01); H10D 84/03 (2025.01); H10D 88/00 (2025.01)
CPC H10D 30/6735 (2025.01) [H10D 30/6757 (2025.01); H10D 62/118 (2025.01); H10D 64/258 (2025.01); H10D 84/038 (2025.01); H10D 88/00 (2025.01); H10D 88/01 (2025.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
a first transistor comprising a first channel structure positioned over a substrate, first source/drain (S/D) regions positioned on ends of the first channel structure, and a first gate structure disposed all around the first channel structure; and
a second transistor comprising a second channel structure positioned over the first channel structure, second S/D regions positioned on ends of the second channel structure, and a second gate structure disposed all around the second channel structure,
wherein the second channel structure has a smaller dimension than the first channel structure in a horizontal direction substantially parallel to a working surface of the substrate.